The present invention relates to an analog-to-digital conversion device for converting an analog signal into a digital signal, a binary code.
As a conventional ultra-high-speed analog-to-digital converter (analog-to-digital conversion device), for example, a parallel comparison type (flash type) analog-to-digital converter, like the one shown in FIG. 20, has been used (reference: Kazuo Kurokawa, Comp., "Analog IC Application Handbook", Industrial Investigation Committee, 1976, p. 333"). This analog-to-digital converter is constituted by voltage comparison circuits for comparing the magnitude of an analog input signal with a plurality of reference voltages prepared in advance and outputting each result in the form of a binary signal representing "0" or "1", and conversion circuits for encoding the respective binary outputs into a common binary code.
More specifically, the converter shown in FIG. 20 has been proposed as a 4-bit parallel comparison type analog-to-digital converter designed to convert an analog signal V.sub.in into a 4-bit binary code. This converter includes 16 (=4.sup.2) voltage comparison circuits C.sub.1 to C.sub.16 having input terminals. The analog signal V.sub.in from an input terminal T1 is supplied to one input terminal of each voltage comparison circuit.
This converter also has 16 voltage-dividing resistors R.sub.1 to R.sub.16 connected in series between power supply terminals E1 and E2. Each of reference voltages obtained at the nodes of the resistors R.sub.1 and R.sub.2, R.sub.2 and R.sub.3 . . . , R.sub.15 and R.sub.16 is applied to the other input terminal of a corresponding voltage comparison circuit (C.sub.1 to C.sub.15). In addition, a reference voltage obtained on the opposite side of the resistor R.sub.16 to the resistor R.sub.15 is applied to the other input terminal of the voltage comparison circuit C.sub.16.
This converter also includes 15 (4.sup.2 -1) NOR circuits NOR.sub.1 to NOR.sub.15 each having two input terminals. These NOR circuits are connected as follows.
First of all, the negative output from the voltage comparison circuit C.sub.1 and the positive output from the voltage comparison circuit C.sub.2 are supplied to the two input terminals of the NOR circuit NOR.sub.1.
The negative output from the voltage comparison circuit C.sub.2 and the positive output from the voltage comparison circuit C.sub.4 are supplied to the two input terminals of the NOR circuit NOR.sub.2.
The negative output from the voltage comparison circuit C.sub.3 and the positive output from the voltage comparison circuit C.sub.4 are supplied to the two input terminals of the NOR circuit NOR.sub.3.
The negative output from the voltage comparison circuit C.sub.4 and the positive output from the voltage comparison circuit C.sub.8 are supplied to the two input terminals of the NOR circuit NOR.sub.4.
The negative output from the voltage comparison circuit C.sub.5 and the positive output from the voltage comparison circuit C.sub.6 are supplied to the two input terminals of the NOR circuit NOR.sub.5.
The negative output from the voltage comparison circuit C.sub.6 and the positive output from the voltage comparison circuit C.sub.8 are supplied to the two input terminals of the NOR circuit NOR.sub.6.
The negative output from the voltage comparison circuit C.sub.7 and the positive output from the voltage comparison circuit C.sub.8 are supplied to the two input terminals of the NOR circuit NOR.sub.7.
The negative output from the voltage comparison circuit C.sub.8 and the positive output from the voltage comparison circuit C.sub.16 are supplied to the two input terminals of the NOR circuit NOR.sub.8.
The negative output from the voltage comparison circuit C.sub.9 and the positive output from the voltage comparison circuit C.sub.10 are supplied to the two input terminals of the NOR circuit NOR.sub.9.
The negative output from the voltage comparison circuit C.sub.10 and the positive output from the voltage comparison circuit C.sub.12 are supplied to the two input terminals of the NOR circuit NOR.sub.10.
The negative output from the voltage comparison circuit C.sub.11 and the positive output from the voltage comparison circuit C.sub.12 are supplied to the two input terminals of the NOR circuit NOR.sub.11.
The negative output from the voltage comparison circuit C.sub.12 and the positive output from the voltage comparison circuit C.sub.16 are supplied to the two input terminals of the NOR circuit NOR.sub.12.
The negative output from the voltage comparison circuit C.sub.13 and the positive output from the voltage comparison circuit C.sub.14 are supplied to the two input terminals of the NOR circuit NOR.sub.13.
The negative output from the voltage comparison circuit C.sub.14 and the positive output from the voltage comparison circuit C.sub.16 are supplied to the two input terminals of the NOR circuit NOR.sub.14.
The negative output from the voltage comparison circuit C.sub.15 and the positive output from the voltage comparison circuit C.sub.16 are supplied to the two input terminals of the NOR circuit NOR.sub.15.
This analog-to-digital converter includes an OR circuit OR.sub.1 having eight input terminals, an OR circuit OR.sub.2 having four input terminals, and an OR circuit OR.sub.3 having two input terminals. The outputs from the NOR circuits NOR.sub.1, NOR.sub.3, NOR.sub.5, NOR.sub.7, NOR.sub.9, NOR.sub.11, NOR.sub.13, and NOR.sub.15 are supplied to the eight input terminals of the OR circuit OR.sub.1. The outputs from the NOR circuits NOR.sub.2, NOR.sub.6, NOR.sub.10, and NOR.sub.14 are supplied to the four input terminals of the OR circuit OR.sub.2. The outputs from the NOR circuits NOR.sub.4 and NOR.sub.12 are supplied to the two input terminals of the OR circuit OR.sub.3.
In this analog-to-digital converter, the output from the OR circuit OR.sub.1 is output as the first (least significant) bit of a 4-bit binary code B to a bit terminal b4. Similarly, the output from the OR circuit OR.sub.2 is obtained as the second bit of the binary code B at a bit terminal b3. The output from the OR circuit OR.sub.3 is obtained as the third bit of the binary code B at a bit terminal b2. The output from the NOR circuit NOR.sub.8 is obtained as the fourth (most significant) bit of the binary code B at a bit terminal b1.
According to the above analog-to-digital converter, the analog signal V.sub.in can be converted into the binary code B consisting of the four bits at the bit terminals b4 to b1.
In the above conventional analog-to-digital converter, however, to convert the analog signal V.sub.in into the 4-bit binary code B, the following many elements are required: the 16 voltage comparison circuits C.sub.1 to C.sub.16, the 16 resistors R.sub.1 to R.sub.16, the 15 NOR circuits NOR.sub.1 to NOR.sub.15, and the three OR circuits OR.sub.1 to OR.sub.3.
When, therefore, the conventional analog-to-digital converter and other circuit devices are to be integrated into a monolithic unit on one substrate, the analog-to-digital converter occupies a large area, interfering with an increase in integration degree. In addition, since many elements are required, the power consumption becomes large. This inhibits an increase in operation speed.